Successive Approximation (SA) is a popular analog-to-digital conversion scheme. Various types of SA Analog-to-Digital Converters (ADCs) are known in the art. For example, Chen et al. describe a power-efficient Signal-to-Noise Ratio (SNR) enhancement for SA ADCs, in “A 10.5-b ENOB 645 nW 100 kS/s SAR ADC with Statistical Estimation Based Noise Reduction,” Proceedings of the 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, Calif., Sep. 28-30, 2015.
A SAR ADC configuration having two comparators is described by Giannini et al., in “An 820 uW 9b 40 MS/s Noise-Tolerant Dynamic-SAR ADC in 90 nm Digital CMOS,” IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, February, 2008, pages 238-239.
Venca et al. describe another SAR ADC configuration, in “A 0.076 mm2 12b 26.5 mW 600 MS/s 4×-Interleaved Subranging SAR-ΔΣ ADC with On-Chip Buffer in 28 nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, February, 2016, pages 470-471. Yet another SAR ADC scheme is described by Liu et al., in “A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS,” IEEE Journal of Solid-State Circuits, Volume 50, No. 11, November 2015.
The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.